Embodiments of the present invention relate generally to integrated circuits (ICs). More particularly, embodiments of the present invention relate to loopback testing techniques that may be implemented in an IC (e.g., a programmable logic device) having a transceiver with a single stage equalizer in the receiver channel.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms. For instance, a programmable logic device (PLD) may be an integrated circuit that may be programmed (e.g., configured) to provide a desired functionality that the PLD is designed to support. Generally, PLDs may include programmable blocks of logic, input/output (I/O) logic, as well as high-speed communication circuitry. For instance, the high-speed communication circuitry may include high-speed transceiver channels through which the PLD may transmit serial data to and/or receive serial data from circuitry that is external to the PLD. Accordingly, the high-speed communication circuitry may support any of various desired communication protocols.
For testing purposes, transceiver channels may incorporate several internal loopback testing schemes in which different signal paths may be tested in order to identify weak spots in a particular design and to narrow down or pin-point on-die and/or chip-to-chip issues. One such loopback mode is a serial loopback mode, wherein full-swing serialized data from the transmitter (TX) side of the transceiver channel is brought to the receiver (TX) channel and outputted via the output pins of the receiver (RX) side. In RX designs having multiple equalizer stages, the final equalizer stage may remain powered on during loopback testing while all preceding equalizer stages are powered off. Thus, the loopback signal may pass through the final equalizer stage and onto the RX output pins, where it may be passed to logic further downstream. In this case, inputs to the RX input pins could continue to toggle without impacting the loopback path performance, since all intermediate equalizer stages upstream from the final equalizer stage are powered off, thus insulating the RX input pins from the loopback path.
Unfortunately, in certain IC designs, such as those where the equalizer logic of the receiver side of a transceiver channel may be reduced or simplified to a single stage, serial loopback testing may be more challenging. For instance, since there are no additional equalizer stages that may be used to isolate the loopback path from the RX input pins in a single stage design, toggling of the RX input pins may generate capacitive coupling at the RX output pins, which may negatively impact the loopback signal.